The cost to semiconductor manufacturers of replacing chip sets and other semiconductor devices after they have been incorporated into customer products is significantly larger than the cost of identifying defective devices at the fabrication level and removing them from the product stream. For example, once a defective semiconductor device is incorporated into a product, the product manufacturer must either scrap or rework the product (if the defect is detected at the manufacturing level), or initiate a product recall. In either case, a significant reduction in value of the product results. Consequently, semiconductor devices are typically subjected to rigorous testing at the fabrication level to identify and eliminate defective devices.
Traditional semiconductor manufacturing test methods typically involve subjecting a semiconductor device to thermal stress (termed a “burn in”), after which the device is tested for defects. The thermal stress typically takes the form of a thermal cycle defined by a maximum temperature (TMAX) and a minimum temperature (TMIN), though in some instances, the temperature of the testing chamber may simply be ramped to either a TMAX or TMIN value. Using such techniques, a small but significant percentage of defective devices remain undetected and fail during the first application usage. Such failures, termed in the art as Early Life Failures, represent a significant cost in the manufacture of semiconductor devices and the products which utilize them.
There is thus a need in the art for a method for testing semiconductor devices at the fabrication point which will successfully identify a larger percentage of defective devices, and which will reduce or eliminate the incidence of early life failures. There is also a need in the art for a fabrication process which incorporates such testing methods. These and other needs may be met by the devices and methodologies described herein.